FIG. 1 shows a conventional source synchronous communications system 100 for data communications between a first low speed data processor 102 and a second low speed data processor 104. A plurality of high speed data channels including a first high speed data channel 106, a second high speed data channel 108, and so on, up to an Nth high speed data channel 110, are coupled between a source synchronous transmitter 112 and a source synchronous receiver 114.
The data processors 102 and 104 are “low speed” in that they generate V-bits of parallel data bits at a frequency that is V-times lower than the frequency of serial data transmission through the “high speed” data channels 106, 108, and 110. The source synchronous transmitter 112 serializes the parallel V-bits for serial data transmission through the data channels 106, 108, and 110. Thus, the source synchronous transmitter 112 is comprised of a respective transmitter serializer for each of the high speed data channels 106, 108, and 110.
A first transmitter serializer 116 receives a first parallel V-bits from the first low speed data processor 102 and serializes such V-bits to generate serial data bits SDOUT1 transmitted via the first high speed data channel 106. Similarly, a second transmitter serializer 118 receives a second parallel V-bits from the first low speed data processor 102 and serializes such V-bits to generate serial data bits SDOUT2 transmitted via the second high speed data channel 108. In addition, an Nth transmitter serializer 120 receives an Nth parallel V-bits from the first low speed data processor 102 and serializes such V-bits to generate serial data bits SDOUTN transmitted via the Nth high speed data channel 110.
A transmitter PLL (phase locked loop) 122 receives a transmit clock signal, from the first low speed data processor 102, that is synchronized with each of the V-bits generated for the transmitter serializers 116, 118, and 120. For example, each of the V-bits is generated for the transmitter serializers 116, 118, and 120 for every clock cycle of the transmit clock signal from the first low speed data processor 102. The transmitter PLL 122 generates a high speed transmit clock signal (HSTCLK) with a frequency that is V-times the frequency of the transmit clock signal from the first low speed data processor 102.
Each of the transmitter serializers 116, 118, and 120 uses HSTCLK from the transmitter PLL 122 to generate the serial data bits SDOUT1, SDOUT2, and SDOUTN from the respective parallel V-bits. In addition, each of the high speed data channels 106, 108, and 110 transmits the serial data bits SDOUT1, SDOUT2, and SDOUTN at the higher frequency of HSTCLK.
The transmitter PLL 122 also generates a transmitted clock signal (CLKOUT) that is transmitted via a clock data channel 124. CLKOUT has the lower frequency of the transmit clock signal from the data processor 102 and is synchronized with the serial data bits SDOUT1, SDOUT2, and SDOUTN. For example, V-bits of the serial data bits SDOUT1, SDOUT2, and SDOUTN may be generated every cycle of CLKOUT. Thus, the transmitted data bits SDOUT1, SDOUT2, and SDOUTN and the transmitted clock signal CLKOUT are termed “source synchronous”. In addition, the high speed data channels 106, 108, and 110 and the synchronized clock signal CLKOUT comprise a “source synchronous link group”.
A plurality of receiver deserializers comprise the source synchronous receiver 114 including a first receiver deserializer 126, a second receiver deserializer 128, and so on, up to an Nth receiver deserializer 130. In addition, a receiver PLL (phase locked loop) 132 receives a received clock signal CLKIN which is the transmitted clock signal CLKOUT transmitted via the clock data channel 124. The receiver PLL 132 generates a high frequency sampling clock signal SCLK to be used by each of the receiver deserializers 126, 128, and 130 for sampling a respective received data signal. The frequency of SCLK is V-times the frequency of the received clock signal CLKIN.
Received serial bits data signals SDIN1, SDIN2, and SDINN are the transmitted serial data bits SDOUT1, SDOUT2, and SDOUTN, respectively, transmitted via the high speed data channels 106, 108, and 110, respectively. The first receiver deserializer 126 samples the first received serial bits data signal SDIN1 using SCLK to generate a parallel V-bits data signal for the second low speed data processor 104. Similarly, the second receiver deserializer 128 samples the second received serial bits data signal SDIN2 using SCLK to generate a parallel V-bits data signal for the second low speed data processor 104. In addition, the third receiver deserializer 130 samples the Nth received serial bits data signal SDINN using SCLK to generate a parallel V-bits data signal for the second low speed data processor 104.
The receiver PLL 132 also generates a parallel data clock signal that is the low speed received clock signal CLKIN delayed by a predetermined time period. The parallel data clock signal is synchronized with the parallel V-bits generated by the receiver deserializers 126, 128, and 130 and is used by the second low speed data processor 104 for processing such parallel V-bits from the receiver deserializers 126, 128, and 130.
FIG. 2 shows the components within the transmitter PLL 122 and within one of the transmitter serializers 116, 118, or 120, such as the Nth transmitter serializer 120 for example. The transmitter serializer 120 is comprised of a parallel to serial shift register 134, and the transmitter PLL 122 is comprised of a xV frequency multiplier 136 and a 1/V frequency divider 138. FIG. 3 shows a timing diagram during operation of the transmitter serializer 120 and the transmitter PLL 122 of FIG. 2.
Referring to FIGS. 2 and 3, a symbol comprised of the parallel V-bits, TD<1:V>140 in FIG. 3 and the low frequency transmit clock signal 142 are generated by the first low speed data processor 102. The shift register 134 uses an edge of the transmit clock signal 142 for loading in the symbol of the parallel V-bits. For example, an Nth symbol of the parallel V-bits 140 is loaded into the shift register at a rising edge 144 of a cycle 152 of the transmit clock signal 142.
The xV frequency multiplier 136 generates HSTCLK 146 in FIG. 3 by multiplying the frequency of the transmit clock signal 142 by V-times. In addition, the 1/V frequency divider generates CLKOUT 148 in FIG. 3 by dividing the frequency of HSTCLK 146 by V-times. Thus, the frequency of CLKOUT 148 is substantially same as the frequency of the transmit clock signal 142.
In addition, the shift register 134 uses HSTCLK 146 to shift out the bits within the shift register 134 as the serial data bits SDOUT 150. For example, referring to FIGS. 2 and 3, each serial bit of SDOUT 150 is shifted out at each rising edge of HSTCLK 146. The symbol of V-bits shifted out as serial data bits is synchronized to an edge of the transmit clock signal 142 and thus of CLKOUT 148. For example in FIG. 3, the Nth symbol of V-bits is generated as the serial data bits SDOUT 150 after two cycles of HSTCLK 146 (i.e., with two bits of delay) after the rising edge 144 of the transmit clock 142 or of CLKOUT 148. Such a delay is typically to account for the sample and hold time during loading of the Nth symbol of V-bits into the shift register 134 at the rising edge 144. Nevertheless, the serial data output signal SDOUT 150 is synchronized with the transmitted clock signal CLKOUT 148.
Such a parallel to serial shift register 134, xV frequency multiplier 136, and 1/V frequency divider 138 are each individually known to one of ordinary skill in the art of electronics. In addition, each of the transmitter serializers 116, 118, and 120 has a respective parallel to serial shift register similar to the shift register 134 of FIG. 2 that each uses the one HSTCLK from the transmitter PLL 122 for generating the respective serial data bits SDOUT1, SDOUT2, and SDOUTN.
FIG. 4 shows the components within the receiver PLL 132 and within one of the receiver deserializers 126, 128, and 130 such as the Nth receiver deserializer 130 for example. The receiver deserializer 130 is comprised of a serial to parallel shift register 162, and the receiver PLL 132 is comprised of a xV frequency multiplier 164 and a re-timer 166. FIG. 5 shows a timing diagram during operation of the receiver deserializer 130 and the receiver PLL 132 of FIG. 4.
Referring to FIGS. 4 and 5, the xV frequency multiplier 164 generates SCLK 174 by multiplying the frequency of CLKIN 172 by V-times. In addition, the shift register 162 uses SCLK 174 to sample in and shift SDIN 176 at every rising edge of SCLK 174. The re-timer 166 generates the parallel data clock signal 178 by delaying CLKIN 172 a predetermined time period using SCLK 174.
The shift register 162 also uses the parallel data clock signal 178 for shifting out a symbol of parallel V-bits RD<1:V>180, at every rising edge of the parallel data clock signal 178. The re-timer 166 determines the timing of the rising edge of the parallel data clock signal 178 to ensure that the V-bits of a symbol are stabilized within the shift register 162 before being shifted out to the second low speed data processor 104. For example, a symbol of V-bits as sampled by the shift register 162 is two-bits delayed from a rising edge of CLKIN, and the re-timer is designed for such a known delay. At any rate, the received serial bits data signal SDIN 176 and the received clock signal CLKIN 172 are synchronized such that CLKIN 172 is used for defining the symbol boundaries of the V-bits.
Such a serial to parallel shift register 162, xV frequency multiplier 164, and re-timer 166 are each individually known to one of ordinary skill in the art of electronics. In addition, each of the receiver deserializers 126, 128, and 130 has a respective serial to parallel shift register similar to the shift register 162 of FIG. 4 that each uses the one SCLK from the receiver PLL 132 for sampling the respective received serial bits data signal SDIN1, SDIN2, or SDINN.
Referring to FIGS. 1, 5, and 6, the received clock signal CLKIN 172 and the received serial bits data signal SDIN 176 are transmitted via different data channels. Each of such different data paths is likely to have different delays such that CLKIN 172 and SDIN 176 are skewed. Referring to FIGS. 5 and 6, SCLK 174 is generated from CLKIN 172 with a rising edge of CLKIN 172 being aligned to a falling edge of SCLK 174. In that case, each rising edge of SCLK 174 is used for sampling SDIN 176.
FIG. 6 illustrates an ideal SDIN 182 that is not skewed with respect to the received clock signal CLKIN 172. The ideal SDIN 182 has a stable bit time 184 during which the bit value does not change within a total bit time 186. On the other hand, the value of SDIN 182 jitters within the bit time 186 out-side of the stable bit time 184 (as indicated by the cross-hatching in FIG. 6) and may change in bit-value with such jitter. The stable bit time 184 is typically about 50% of the total bit time 186.
For the ideal SDIN 182, the rising edge of SCLK 174 occurs substantially at the center of the stable bit time 184 such that a valid bit value is sampled. FIG. 6 also illustrates a skewed SDIN 188 that is skewed from CLKIN 172 by a skew time period 190. With such a skewed SDIN 188, the rising edge of SCLK 174 occurs during jitter of the skewed SDIN 188 such that the sampled bit value may not be valid.
Nevertheless, referring to FIG. 1, since the received clock signal CLKIN and the received serial bits data signal SDIN are transmitted via different data channels, such skew between such signals is likely to occur. For example, assume that SDIN is transmitted at 1 Gbps (giga-bits per second) such that each bit time is 1000 ps (pico-seconds) and such that the stable bit time 184 is 500 ps. In addition, assume that the serial to parallel shift register 162 requires a set-up and hold time of 100 ps for sampling the bit value. In that case, a skew of +/−200 ps may be tolerated by the source synchronous receiver 114 of the prior art. However, each of the data channels 106, 108, 110, and 124, which are typically comprised of PC board traces, connectors, termination resistors, and/or cables, may contribute more than the tolerated skew such as even a skew of over 30 ns (nano-seconds).
Thus, a mechanism is desired for accounting for the skew between the received clock signal CLKIN and the received serial bits data signal SDIN for sampling valid data bits of SDIN.